In a trench gate MOS field effect transistor (MOSFET), reduction of on resistance due to reduction of cell pitch can be expected with respect to the planer gate MOSFET. In a trench gate MOSFET using a wide band gap semiconductor such as silicon carbide (SiC) as a material, a high voltage is easily applied to a gate insulating film located at the bottom of a trench, and thus, there is a concern that the gate insulating film may be broken.
A structure in which a p+-type region is provided at the bottom of the trench and a p+-type region is provided below a contact region between the trenches so as to relax the electric field intensity at the bottom of the trench has been proposed. In this case, when a reverse bias is applied, it is important to allow the avalanche current to relatively more easily flow in the p+-type region below the contact region than the p+-type region at the bottom of the trench.
Therefore, it is considered that an n+-type region is selectively formed under the p+-type region below the contact region to concentrate the electric field on the p+-type region below the contact region so as to allow the avalanche current to relatively easily flow. However, since the electric field concentrates locally on the p+-type region below the contact region, there is a problem that the breakdown voltage of an active area is decreased and the breakdown voltage margins of the peripheral area and the active area are decreased.
In addition, JP 3943054 B2 discloses a structure in which a p-type electric field relaxation region below a p-type contact region is arranged to be separated from a channel region in a trench gate MOSFET. JP 2001-313393 A discloses a structure in which a plurality of p-type buried regions are arranged below a p-type base layer in a power MOSFET. US 2008/0,185,593 A discloses a structure in which a plurality of p-type implantation regions are provided below a source region in a SiC planar MOSFET. JP 2013-21447 A discloses a structure in which a plurality of p-type semiconductor layers are provided below a contact region in a SiC planar MOSFET.